Metal Semiconductor Field Effect Transistors (MESFETs) are becoming more ubiquitous in modern electronics and are particularly applicable in high speed and high voltage analog and digital electronics applications. As illustrated in FIG. 1A, a typical MESFET 10 includes a channel region 12 that extends between a source region 14 and a drain region 16. A Schottky gate structure 18 includes a gate contact 20 that resides over the channel region 12 and between a source contact 24 that resides over the source region 14 and a drain contact 22 that resides over the drain region 16. The source region 14 and the associated source contact 24 are collectively referred to as a source 28. The drain region 16 and the associated drain contact 22 are collectively referred to as a drain 26. In a silicon-on-insulator (SOI) process, the channel region 12, the source region 14, and the drain region 16 are formed in a silicon layer 30 that resides over an insulator layer 32, which is formed from a buried oxide or like dielectric, and an underlying substrate 34, which may also be formed from silicon. In a typical n-channel MESFET 10, the source region 14 and the drain region 16 are generally heavily doped with N-type material, the channel region 12 is either unintentionally doped or lightly doped with N-type material, and the substrate 34 is doped with either P-type or N-type material. A depletion layer (not illustrated) that naturally forms in the channel region 12 effectively controls the flow of current between the drain 26 and the source 28. In operation, varying the voltage applied to the gate contact 20 varies the thickness of the depletion layer, and thus varies the flow of current between the drain 28 and the source 26.
In most Complementary Metal Oxide Semiconductor (CMOS) processes, the source, gate, and drain contacts 22, 20, and 24 are often formed from a silicide. Silicide source and drain contacts are formed by applying a reactive metal, such as cobalt, nickel, or the like, on the silicon layer 30 where contacts are desired. The metal reacts with the silicon to form a silicide contact. The reaction effectively consumes a portion of the silicon such that the resulting silicide contact extends into the silicon layer 30. Typically, the thickness ts of the silicon layer 30 is generally at least 200 nanometers (nm) thick. Notably, the silicide gate contact 20 consumes a significant fraction of the silicon layer 30 that resides below the gate contact 20. As a result, the effective thickness tc of the channel region 12 is substantially less than the thickness ts of the silicon layer 30. When the thickness ts of the silicon layer 30 is 200 nm or more, the effective thickness tc of the channel region 12 is sufficiently thick to allow current to flow between the drain 28 and the source 26, as well as form and control an effective depletion layer in response to varying a voltage applied to the gate contact 20 to control the current flow in the channel region 12.
Unfortunately, the continuous pressure to reduce component sizes and increase integration has led to a continual reduction in the thickness of the silicon layer 30 in which MESFETs and other devices are formed. A MESFET 10 is illustrated in FIG. 1B, wherein the thickness ts of the silicon layer 30 has been substantially reduced with respect to that illustrated in FIG. 1A. As is clear from the illustration, the thickness tc of the channel region 12 is very small.
A thin channel region 12 poses two major manufacturing and design issues. First, when the drain, gate, and source contacts 22, 20, and 24 are silicide contacts, the process of forming the silicide is difficult to control. In particular, the extent in which the silicon layer 30 is consumed when the silicide is being formed is difficult to predict, and as such, the drain, gate, and source contacts 22, 20, and 24 may extend completely through the silicon layer 30, thereby leaving no silicon for the channel region 12 beneath the gate contact 20. Even when sufficient silicon remains beneath the gate contact 20 for the channel region 12, the relative variability of the thickness tc of the channel region 12 results in undesired performance variability. Second, even if the depth of the gate contact 20 could be tightly controlled, the MESFET 10 will not perform as desired once the thickness tc of the channel region 12 becomes too small. For example, when the thickness ts of the silicon layer 30 is 60 nm or less and the thickness tc of the channel region 12 is about 30 nm or less, the channel region 12 may not conduct, and thus allow no current to flow, unless there is a relatively large positive voltage applied to the gate contact 20. When a relatively large positive voltage is applied to the gate contact 20, the gate voltage is so high that the MESFET 10 behaves like a diode instead of a transistor, wherein current flows from the gate contact 20 to the source contact 24 before current begins flowing between the drain 26 and the source 28. Accordingly, there is a need for a MESFET architecture that can be formed using CMOS or other processes that employ relatively thin device layers.